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1. abstract nowadays, many applications, such as automotive exterior and interior lights, display and signage lighting and incandescent bulbs, are going to be replaced more and more by led lamps. this is due to a number of advantages that make the use of this kind of lighting very attractive. above all, leds have an almost unlimited working life, as well as a smaller size and better efficiency, when compared to their incandescent counterparts. moreover, leds have an extremely fast response. they do not require a warm up phase like conventional bulbs do (about 200ms). this ensures added safety especially when used for stoplights. the objective of this application note is to provide a complete explaination of how the stlc1, a monolithic device, is able to drive up to three led lamps clusters at the same time. 2. general device description. figure 1: stlc1 internal block diagram st-l tl-l - + tr-l b+ turn stop tail oscillator pwm switch contoller - + 1.24v thermal protection cntl ts-pwm lamp outage detect pulse width controller p-out tr-drv ref fdbk st-drv tl-drv ref gnd lmp-out osc comp1 r s err amp m1 m2 m3 i n p u t pwm comp december 2001 1/12 AN1488 application note stlc1 led cluster lamp driver f. macina (dsg v regs application engin eer)
AN1488 - application note 2/13 stlc1 is basically a fixed frequency fully monolithic switching regulator primarily intended for buck-boost and sepic (single ended primary inductor current) configurations, with three independent smart low side drivers (lsds), control logic for monitoring lamp fault conditions. it also has a thermal shutdown protection with hysteresis to prevent device overheating. figure 1 shows the internal block diagram. the stlc1 operates at an internally fixed switching frequency of about 180khz allowing the user to minimize the number of external components and also allowing smaller sized filter components than what would be needed with a lower frequency switching regulator. the pwm controller has an internal current mode control scheme and the converter's output voltage regulation can be achieved with a simple resistive divider network. the cycle-by-cycle current limitation, the programmable output over-current protection and the device input over-voltage protections give easy and robust design solutions. 3. pin connections and descriptions. stlc1 is housed in a powerso-20 ? package for smd assembly. device pin out is reported in figure 2 and table 1 briefly summarizes the device pin functionality. figure 2: stlc1 device pinout gnd tr-drv tr-l st-drv st-l tl-drv tl-l cntl ref gnd gnd lmp-out ts-pwm p-out fdbk turn stop tail b+ gnd 120 11 3 4 5 6 7 8 9 10 2 12 13 14 15 16 17 18 19
AN1488 - application note 3/13 table 1: stlc1 pin functions pin # name function 1 gnd ground 2 tr-drv the low side driver drain pin for the turn led array 3 tr-l the low side driver source pin, used to detect either a lamp outage or an over-current condition for the turn led array 4 st-drv the low side driver drain pin for the stop led array 5 st-l the low side driver source pin, used to detect either a lamp outage or an over-current condition for the stop led array 6 tl-drv the low side driver drain pin for the tail led array 7 tl-l the low side driver source pin, used to detect either a lamp outage or an over-current condition for the tail led array 8 cntl determines, according to a percentage of the v ref , the pulse width con- troller internal oscillator duty cycle 9 ref stable reference voltage 10 gnd ground 11 gnd ground 12 b+ stlc1 power supply 13 tail tail input pin. when brought high, tail activates the ic and drives the tail led array 14 stop stop input pin. when brought high, stop activates the ic and drives the stop led array 15 turn turn input pin. when brought high, turn activates the ic and drives the turn led array 16 fdbk internal error amplifier inverting pin 17 p-out power mosfet drain pin 18 ts-pwm a three state input. it determines the control logic for tail and stop low side drivers. 19 lmp-out a weak pulled up signal during lamps no fault condition and an active pull down when a fault condition is detected 20 gnd ground
AN1488 - application note 4/13 4. detailed internal block diagram description. in the following sections a detailed description of each block composing the device will be given. figure 3: stlc1 typical application diagram 4.1 smps power and control section. the n-channel power mosfet, the pwm switch controller, the voltage comparators comp1 and pwm comp, the error amplifier and the internal stable voltage reference ref compose this section. the smps switch is source-grounded via a sensing resistor r s whose purpose is both to perform a cycle-by- cycle power switch current limitation and to provide a ramp voltage for a current mode control. cycle-by- cycle limitation controls the maximum allowable current into the power switch: if the voltage drop on r s , due to the current flowing through it, exceeds an internal fixed value the power mosfet is shut-off until the next switching cycle occurs. the output voltage regulation is performed using a current mode control scheme without the need of any compensation network. this allows the user to drastically reduce the number of external components. the output voltage is feedback to the fdbk pin device by means of an external resistor divider. the difference between the sampled output voltage and an internal stable bipolar band-gap voltage (error signal) is amplified and then compared with a sawtooth voltage, provided by the sensing resistor r s times the inductor current whose typical frequency is 180khz. when the amplified error signal, which varies very slowly with time relative to the switching frequency, is greater than the sawtooth waveform, the power switch is kept on. otherwise, the switch is off. 4.2 supply section. stlc1 is powered from the b+ pin. input supply voltages greater than 29v (typical) cause the over voltage protection to act, shutting down the device. gnd lmp-out ts-pwm p-out fdbk turn stop tail b+ gnd iout turn tail stop rlr rls rlt gnd tr-drv tr-l st-drv st-l tl-drv tl-l cntl ref gnd r tr r ts r tt rc1 rc2 c ref ip-out c sepic c out out rf1 rf2
AN1488 - application note 5/13 4.3 input buffer section. figure 4: start-up phase and input signal timing diagram (with ts-pwm floating) figure 5: magnified start-up phase (ts-pwm floating) tail turn stop lsd turn current lsd stop current lsd tail current p-out out v ref t t t t t t t t t t pulse width controller internal oscillator frequency v b+ v turn lsd turn current v ref v out 0.1v out t smps-on 0.95v ref the same diagram appears if only stop or tail are activated instead of turn i 0.95v out t lsd-on t lsd-off t t t t t not to scale
AN1488 - application note 6/13 turn, stop and tail are the ic's inputs. these inputs are internally connected to a pull-down and they are active when held high (e.g. connected to b+). if all inputs are disabled, smps and most of the internal control and diagnostic circuitry are in idle state. this is done in order to maintain the stand-by quiescent current below very low values, strengthening the battery life in case stlc1 is powered from such a power source. when only one of these inputs is activated, a device start-up phase begins. first the c ref capacitor is charged and, as soon as the voltage on it has reached about 95% of its steady state value (v ref ), the smps starts switching. in order to allow the output to reach the regulated voltage value faster, the lsd corresponding to the input just enabled will only conduct when the out voltage is about 95% of its final value. if more than one input is active at the same time, this start-up phase does not take place. figure 4 shows this start-up phase. 4.4 low side driver control section. the pulse width controller internally drives the stop and tail lsds, while the external turn input pin directly drives the corresponding lsd. the pulse width controller has two inputs: ts-pwm and cntl. table 2: ts-pwm control pin truth table ts-pwm input sets, according to the truth table shown in table 2, the control logic for stop and tail lsd drivers. cntl can be used instead to change the duty cycle of the pulse width controller's internal oscillator, performing an led's dimming. forcing the cntl pin voltage to be a fraction of v ref varies the duty cycle of the internal oscillator. this is simply feasible by using a resistor divider. the duty cycle percentage can be approximately calculated as follows. drive type ts-pwm pin voltage input activated tail array stop array low (v ts-pwm <0.1v ref ) tail pwm pwm stop off on tail and stop pwm on mid (v ts-pwm =v ref /2 or floating) tail pwm off stop off on tail and stop pwm on high (v ts-pwm >0.98v ref ) tail pwm pwm stop on on tail and stop on on
AN1488 - application note 7/13 duty cycle % = due to the fact that the turn lsd is not controlled by the pulse width controller, internal dimming can only be performed on the tail and stop led arrays. the turn array can be externally dimmed (as well as tail and stop) driving the corresponding input with a square pulse signal whose maximum frequency must be 200hz. if only one input is externally dimmed and the remaining two are disabled, keep in mind that every rising edge of the enabling signal triggers a start-up phase (see the detailed 4.3 input buffer section ) and the corresponding lsd conducts with a delay that depends both on the capacitor value between ref and gnd and the filter output capacitor. (see figure 5 t lsd-on ). a high ref to gnd capacitor value is useful to damp the switching noise on the ref pin but gives long start-up times while, on the other hand, low values are useful for faster turn-on time but they have lower switching noise filtering capability. 4.5 thermal protection section. overheating of the device due to an excessive power throughput or insufficient heat sinking is avoided by the thermal shutdown function. in case the junction temperature exceeds approximately 150 c the thermal shutdown protection shuts off the smps, cooling down the device. a thermal hysteresis of 10 c is guaranteed in order to avoid oscillation. 4.6 low side driver (m1, m2, m3) section. the purpose of the low side drivers is to connect, when enabled, each led array to ground creating a path for the current. using external resistors, the current to flow into the led arrays is set according to the following formula: where: r l =r lt ,r ls or r lr (see figure 3) r t =r tt ,r ts or r tr (see figure 3) r (on) =static drain to source lsd on resistance v out =output voltage v array =expected led array voltage drop lsd over-current protection and under-current diagnostic (see 4.7 lamp outage detection section )is performed by sensing the voltage on r t resistors. 4.7 lamp outage detect section. this internal block monitors the current flowing into each lsd, when active, by sensing the voltage drop across the r t (r ts ,r tt ,r tr ) resistors (see figure 3). 3.8 if rc 1 rc 2 rc 2 + ----------------------------- 0.2 v ref ------------ - % rc 1 rc 1 rc 2 + ----------------------------- 100 ? elsewhere i array v out v array () r t r l r on () ++ ------------------------------------------- - = {
AN1488 - application note 8/13 doing this, the lamp outage block is able to detect either an over-current or an under-current (led fail) condition. figure 6: lamp outage section behaviour (not to scale) in fact, in case one or more led fails, the current on the r t resistor will drop due to the increased led array equivalent resistance. if the voltage goes below an internal fixed threshold, a led array fail condition is detected and the lmp-out pin will signal this fault status (lmp-out pin low). in order not to detect false fault conditions, due to the smps switching noise for example, a delay from fault detection to fault indication is guaranteed. for the same reason there is a time delay from the fault removal to the safe indication (lmp-out pin high). for the under-current diagnostic control logic timing see figure 6. on the other hand if the current flowing into one lsd increases, the voltage on r t increases too. an over-current condition is detected when the voltage drop on r t exceeds an internal fixed threshold value. in this case the lsd average current is reduced by switching the corresponding lsd on and off. the lamp outage section is and-ed with each input, that is, a fault condition can be detected only when the led arrays are enabled. 4.8 reference section. the device has an internal temperature stable bipolar band-gap voltage reference whose typical value is 1.24v. the internal logic circuitry is supplied with a voltage derived from the band-gap reference and it is externally available to the ref pin. a capacitor on this pin reduces the noise switching effect on the band-gap voltage reference. 5. general demoboard consideration. the components placed on the stlc1 demoboard, whose schematic is shown in figure 7, have the following purposes: lmp-out turn v b+ rtr resistor voltage t t t t fault on fault off delay from fault detection to indication delay from fault removal to indication
AN1488 - application note 9/13 c5, l1 and c4 are a pi-filter for the supply voltage and with c6 they represent the bulk energy storage elements for stlc1. c16 is a low esr capacitor (x7r dielectric) used to reduce the voltage ripple on the b+ device supply pin. two coupled inductors compose t1, and together with c7 coupling capacitor, they form the so-called sepic topology. this converter configuration combines the best features of both the boost (continuous input current) and flyback topologies (any output voltage) and also reduces the converter ripple input current. figure 7: demoboard application circuit d1 is a power rectifier schottky diode, rated for an average current of 3a and 50v reverse blocking voltage, while c9, l2 and c8 are again a pi-filter for the output voltage and c1 and c2 are low esr capacitors (x7r dielectric). this output filter smoothes output current from the inductor to the load, helps maintain a steady output voltage during transient load changes and reduces the output voltage ripple. these capacitors must be selected with sufficient capacitance (c8, c9) and sufficiently low esr to perform these functions. the output voltage is set by the r10 and r11 resistors according to the following formula: in the proposed demoboard the output voltage is set at about 10v. r15 and c12 are a low pass filter useful to damp the switching noise on the fdbk pin (pin 16). the three couples (r4, r5), (r6, r7) and (r8, r9) are used to limit the current to each lsd, respectively turn, stop and tail (see paragraph 4.6 low side drivers (m1, m2, m3) section ). r4, r6 and r8 have also the function of sensing resistors to detect both under and over current that flows into the corresponding lsd (see paragraph 4.7 lamp outage detect section ). their value is led array module 12 1,10,11,20 2 3 4 5 6 7 8 9 13 14 15 16 17 18 19 to pin 19 + - jp1 jp2 r12 r13 r14 c11 tr1 t1 c7 r18 c18 l1 c5 c4 c6 c16 r16 c14 d1 l2 c1 c9 c8 c2 r10 r11 jp4 r15 c12 r4 r6 r8 jp3 r5 r7 r9 dlp rlp v out v fdbk r 10 r 11 + r 11 -------------------------- =
AN1488 - application note 10/13 chosen as a trade off between the required sensibility in detecting anomolous working conditions (under and over current) and wasted electrical power. c11 is an external bypass reference capacitor, while tr1 is a trimmer used to change the internal pulse width controller's duty cycle (see paragraph 4.4 lsd control section ) by partitioning the reference voltage. dlp is a led diode that turns on when a fault condition is detected; rlp limits the current flowing into the dlp. the rc couple r18, c18 is the simplest, but effective, non-polarized dissipative voltage snubber network. the main advantages of this snubber are that it damps the resonance of paracitic elements in the power circuit, thus reducing emi issues and it also minimizes the power dissipation and stress of the internal power switch at turn off. r16 and c14 are the same kind of snubber network and they are used here to minimize over voltages and to damp voltage ringing, which may result from the reverse recovery current of schottky diode d1 and the leakage inductance. r12, r13 and r14 resistors limit the current flowing into stlc1 inputs when enabled. 6. pcb layout recommendation. any switch mode power supply requires a good design of the pcb (printed circuit board) layout in order to achieve maximum performance in terms of system functionality and emitted radiations. components placing, traces routing and width are the major issues. some fundamental rules will be given so that the pcb designer can produce a good layout. all traces carrying current should be drawn on the pcb as short and thick as possible. this should be done to minimize resistive and inductive parasitic effects, gaining in system efficiency and radiated emissions. current return routing is another crucial issue. signal ground and power ground must be routed separately and connected to a single ground point. as a rule of thumb, traces carrying signal currents should run far away from traces carrying pulsed currents or quickly swinging voltages avoiding any coupling effect between them. every unused space on the pcb could be filled with a ground plane helping to reduce noise emission. some sensitive points of the system, fdbk and p-out pins for example, may require some extra filtering and/or snubbering. in case high frequency filter capacitors are used (with ceramic or plastic film dielectric), they must be placed between these pins and the signal ground, as close to the ic as possible.
AN1488 - application note 11/13 table 3: demoboard application circuit bom figure 8: pcb component outline reference description l1, l2 vk200 c4, c5, c6 22 m f/35v electrolytic capacitor low esr c16 220nf/35v ceramic capacitor x7r dielectric c7 47 m f/35v electrolytic capacitor c1, c2 4.7nf/35v ceramic capacitor x7rdielectric c8, c9 220nf/35v electrolytic capacitor low esr c14 560pf c18 560pf/50v c11 1 m f/35v tantalum capacitor c12 220pf ceramic capacitor r10 9.1k w resistor 0.125w/0.1% r11 1.3k w resistor 0.125w/0.1% r15 4.7k w resistor 0.125w/5% r16 56 w resistor 0.125w/5% r18 10 w resistor 0.125w/5% r12, r13, r14 1.2k w 0.125w/5% r4, r6, r8 2.2 w resistor 1w/5% r5, r7, r9 1 w 1w/5% tr1 10k w trimmer rlp 1.5k w resistor 0.125w/5% d1 schottky diode sts3l4c939 dlp led diode t1 sepic inductor, toroid horizontal tht 20 m h@10adc, 200-250khz jp1, jp2, jp3 jumper 7cm 12cm
AN1488 - application note 12/13 figure 9: pcb top layer figure 10: pcb bottom layer 7. conclusion a new device for rear led lamps driving, stlc1, has been presented. moreover, an in depth description of its functional blocks has been given together with some pcb layout suggestions. 7cm 12cm 7cm 12cm
AN1488 - application note 13/13 information furnished is believed to be accurate and reliable. however, stmicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of stmicroelectronics. specification mentioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. stmicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of stmicroelectronics. the st logo is a registered trademark of stmicroelectronics ? 2001 stmicroelectronics - printed in italy - all rights reserved stmicroelectronics group of companies australia - brazil - canada - china - finland - france - germany - hong kong - india - isreal - italy - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - u.s.a. http://w ww.st.com

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